Systems transmit and receive multimedia content including audio and video data. For multimedia data that includes high-resolution video data and/or high-fidelity audio data, it is desirable to transmit the data in uncompressed digital form. Examples of such multimedia data include High-Definition Multimedia Interface (HDMI) data (e.g., data consistent with HDMI Specification Version 1.4a, published Mar. 4, 2010), Digital Visual Interface (DVI) data (e.g., data consistent with DVI Specification Revision 1.0, published Apr. 2, 1999), DisplayPort data (e.g., data consistent with the VESA DisplayPort Standard Version 1 Revision 1a, published Jan. 11, 2008), and Mobile High-definition Link (MHL) data (e.g., data consistent with MHL 1.0 Specification, published Jun. 30, 2010).
FIG. 1A is a block diagram of a prior art multimedia stream switch. Switch 100 receives a plurality of multimedia streams as input. In this figure, streams 101, 102, 103 and 104 are shown to be received by switch 100.
Switch 100 will output one of the input streams as multimedia output stream 190. The respective input stream is determined by stream select 110. Switch 100 is limited in that a user cannot select audio data from one stream to be output with video data from another stream (e.g., audio data from stream 1 cannot be output with video data from stream 2). Thus, even though a device is operatively connected to an input port of switch 100, a user cannot selectively only watch video or listen to audio sent from the device connected to the input port because switch 100 can control only one multimedia stream at a time.
FIG. 1B is a block diagram of the internal components of prior art multimedia stream switch 100, which includes three main components: multimedia stream decoders (in this figure decoder 121 is shown to receive multimedia stream 101, and decoder 122 is shown to receive multimedia stream 102; it is to be understood that each received multimedia stream has its own decoder), switch matrix 125 and multimedia stream encoder 126. Multimedia stream decoders 121 and 122 extract video data and audio stream internally. Switch matrix 125 then selects multimedia data from one of the ports and transfers them to encoder 126, which combines the video and audio data to generate outgoing multimedia stream 190.
Multimedia stream decoder 121 is shown to include video data extractor 131 (to extract video data 144), audio data extractor 133 and audio data information extractor 132 (it is understood that decoder 122, although not shown, includes similar components). It is understood that the audio and video data included in multimedia streams are transferred by sharing bandwidth. In most multimedia streams, a link clock (shown here as link clock 145) will be included with the audio/video data, where there exists a rational (integer divided by integer) relationship between link clock 145 and the video clock. Thus the regeneration of the video clock may be simply generated from the link clock by using a constant clock divider and multiplier.
However, audio clock regeneration (ACR) requires additional logic (i.e., divider 134 and multiplier 135) because there is no such relationship between link clock 145 and the audio clock. Since the relationship is unknown, information representing the relationship needs to be transferred periodically. This information can be represented by two terms: numerator N (shown as signal 142) and denominator cycle time stamp (CTS) values (shown as signal 140). The relationship between the link clock and audio clock is:faudio=flink*N/CTS 
where faudio is the frequency of the audio clock and flink is the frequency of the link clock 145. Value N 142 is extracted from multimedia data stream 101 via audio data information extractor 132 by referring to the frequency of the audio clock. During N audio clock cycles, which is the same duration of time as one cycle of stamping clock 141 (fstamp=faudio/N), audio data information extractor 132 counts the number of the link clock cycles, which becomes CTS value 140 at the corresponding stamping period. At every stamping clock cycle, both N value 142 and CTS value 140 are transferred to the ACR logic. The ACR logic then recreates audio clock 143 from link clock 145 by using clock divider (by CTS) 134 and clock multiplier (by N) 135. When link clock and audio clock are asynchronous, CTS value 140 may slightly vary at every cycle of stamping clock 141. Audio clock 143 and audio data 147 (extracted from audio data extractor 133) are thus combined via logic 136 to form audio data stream 146.
Switch matrix 125 selects which set of video data, audio data stream and link clock to forward to multimedia stream encoder 126 as video data 180, audio data stream input 182 and link clock 181. Multimedia stream encoder 126 includes audio stream receiver 171 to extract audio clock 187, audio data 185 and N value 184 (e.g., if stream 101 is selected, audio clock 187 will correspond to audio clock 143, and audio data 185 will correspond to audio data 147). Logic 172 may divide audio clock 187 by N value 184, and forward the result to Cycle Time Counter logic 173 to obtain CTS value 183. Data signals 180, 181 and 183-185 may then be processed via logic 174 to format the data into multimedia output stream 190.
Thus, multimedia stream switch 100 requires audio clocks to be regenerated. Phase Locked Loop (PLL) circuitries, such as multiplier 135, are used for each input multimedia stream port to generate an output clock whose phase is related to the phase of the input reference clock signal. PLLs are also used to synthesize the local clock with lower or higher frequency than the input reference clock. For audio clock regeneration, a PLL is used to generate an audio clock that is faster than the stamping clock by the factor N.
The cost of implementing PLL blocks is high. PLL blocks on most high-speed chips pose design and verification challenges. PLL blocks also require large on-chip area and consume large amount of power.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein. An overview of embodiments of the invention is provided below, followed by a more detailed description with reference to the drawings.